Prabhakar Jaiswal

IIT Bombay ICS 29'. SVNIT EE 23'. Engineer. Love Cats.

prof_pic.png

I’m a post graduate student at IIT Bombay, pursuing my Master’s in the Integrated Circuits and Systems program (starting 2026). My interests lie in VLSI and digital IC design, chip architecture, FPGA and ASIC development, embedded systems, and PCB design.

I completed my B.Tech in Electrical Engineering from NIT Surat in 2023. After graduating, I worked for two years as an Automation Engineer at Vedanta, where I gained hands-on industry experience before deciding to pursue research and prepare for GATE, which brought me to IIT Bombay.

Outside of engineering, I’m an avid cat lover, If you like cats too we can be friends otherwise not a chance. Share Cat videos with me and i will share my choclate with you. I also enjoy playing badminton and chess. In free time i explore cyber security (only know how to crack wifi 😭)

news

Jul 22, 2026 Joined the Integrated Circuits and Systems (ICS) M.Tech program at IIT Bombay. 🐾
Mar 31, 2026 Cleared UPSC Engineering Services Examination (ESE) 2026 Prelims — preparing for Mains next.
Mar 27, 2026 Cleared GATE 2026 with scores of 664 (EE) and 617 (EC). 🎉
Jul 01, 2025 Wrapped up my role as Assistant Manager at Vedanta Ltd. to pursue full-time preparation for GATE.
Nov 07, 2015 A long announcement with details

latest posts